IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines

2011 Symposium on VLSI Circuits

Author(s): Ikenaga, Y. ; Nomura, M. ; Suenaga, S. ; Sonohara, H. ; Horikoshi, Y. ; Saito, T. ; Ohdaira, Y. ; Nishio, Y. ; Iwashita, T. ; Satou, M. ; Nishida, K. ; Nose, K. ; Noguchi, K. ; Hayashi, Y. ; Mizuno, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 15 June 2011
Page(s): 186 - 187
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-61284-175-5
ISSN (CD): 2158-5601
ISSN (Electronic): 2158-5636
ISSN (Paper): 2158-5601
Regular:

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica... View More

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