IEEE - Institute of Electrical and Electronics Engineers, Inc. - Modeling the effect of parasitic capacitances on the dead-time distortion in multilevel NPC inverters

2011 IEEE 20th International Symposium on Industrial Electronics (ISIE)

Author(s): Szwarc, K.J. ; Cichowski, A. ; Nieznanski, J. ; Szczepankowski, P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Gdansk, Poland, Poland
Conference Date: 27 June 2011
Page(s): 1,869 - 1,874
ISBN (Electronic): 978-1-4244-9312-8
ISBN (Paper): 978-1-4244-9310-4
ISBN (Online): 978-1-4244-9311-1
ISSN (Paper): Pending
ISSN (Online): Pending
DOI: 10.1109/ISIE.2011.5984442
Regular:

A simple model is derived and verified for evaluating the effect of parasitic capacitances on the dead-time related voltage distortion in multilevel NPC voltage source inverters. The model permits... View More

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