IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design challenges of low-power and high-speed memory interface in advanced CMOS technology

2011 IEEE Symposium on VLSI Technology

Author(s): Frans, Y. ; Schmitt, R. ; Nguyen, N. ; Bhardwaj, S. ; Bronner, G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 2011
Page(s): 110 - 111
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-4244-9949-6
ISSN (CD): 0743-1562
ISSN (Electronic): 2158-9682
ISSN (Paper): 0743-1562
Regular:

Design requirements for low-power and high-speed memory interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low... View More

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