IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design enablement for yield and area optimization at 20 nm and below

2011 IEEE Symposium on VLSI Technology

Author(s): Brotman, A. ; Capodieci, L. ; Liu, B. ; Rashed, M. ; Jongwook Kye ; Kengeri, S. ; Venkatesan, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 2011
Page(s): 108 - 109
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-4244-9949-6
ISSN (CD): 0743-1562
ISSN (Electronic): 2158-9682
ISSN (Paper): 0743-1562
Regular:

There are challenges at 20nm and below to maintain node to node area reduction and also enable a fast yield ramp and high yield to enable cost scaling. GLOBALFOUNDRIES uses special constructs to... View More

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