IEEE - Institute of Electrical and Electronics Engineers, Inc. - An efficient manufacturing technique based on process compact model to reduce characteristic variation beyond process limit for 40 nm node mass production

2011 IEEE Symposium on VLSI Technology

Author(s): Kakehi, K. ; Aikawa, H. ; Tadokoro, T. ; Eguchi, H. ; Hirayu, T. ; Yoshimura, H. ; Asami, T. ; Ishimaru, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 2011
Page(s): 90 - 91
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-4244-9949-6
ISSN (CD): 0743-1562
ISSN (Electronic): 2158-9682
ISSN (Paper): 0743-1562
Regular:

Practical manufacturing technique to reduce characteristic variation of 40 nm CMOS device has been developed. Novel feed-forward (FF) system at gate formation for tight gate length control, and FF... View More

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