IEEE - Institute of Electrical and Electronics Engineers, Inc. - Extraction of 3-D trap position in NAND flash memory considering channel resistance of pass cells and bit-line interference

2011 IEEE Symposium on VLSI Technology

Author(s): Joe, S.M. ; Jung, M.K. ; Lee, J.W. ; Lee, M.S. ; Jo, B.S. ; Bae, J.H. ; Park, S.K. ; Han, K.R. ; Yi, J.H. ; Cho, G.S. ; Lee, J.H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 2011
Page(s): 76 - 77
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-4244-9949-6
ISSN (CD): 0743-1562
ISSN (Electronic): 2158-9682
ISSN (Paper): 0743-1562
Regular:

We have extracted the exact position (xT and yT) and energy of a trap in tunnel oxide which induces RTN by considering the channel resistances of pass cells in floating gate NAND flash memory... View More

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