IEEE - Institute of Electrical and Electronics Engineers, Inc. - A highly manufacturable integration technology of 20nm generation 64Gb multi-level NAND flash memory

2011 IEEE Symposium on VLSI Technology

Author(s): Keun Woo Lee ; Se Kyoung Choi ; Sung Jae Chung ; Hye Lyoung Lee ; Su Min Yi ; Byeong Il Han ; Byung In Lee ; Dong Hwan Lee ; Ji Hyun Seo ; Noh Yong Park ; Hae Soo Kim ; Hyung Seok Kim ; Tae Un Youn ; Keum Hwan Noh ; Min Kyu Lee ; Ju Yeab Lee ; Kwang Hee Han ; Won Sic Woo ; Seok Won Cho ; Seung Cheol Lee ; Sung Soon Kim ; Chan Sun Hyun ; Weon Joon Suh ; Sang Deok Kim ; Myung Kyu Ahn ; Hyeon Soo Kim ; Ki Seog Kim ; Gyu Seog Cho ; Sung Kye Park ; Aritome, S. ; Jin Woong Kim ; Seok Kiu Lee ; Sung Joo Hong ; Sung Wook Park
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 2011
Page(s): 70 - 71
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-4244-9949-6
ISSN (CD): 0743-1562
ISSN (Electronic): 2158-9682
ISSN (Paper): 0743-1562
Regular:

Multi-level NAND flash memories with a 20nm design rule have been successfully developed for the first time. A 20nm rule wordline (WL) and bitline (BL) direction have been realized by Spacer... View More

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