IEEE - Institute of Electrical and Electronics Engineers, Inc. - VHDL Environment for Floating Point Arithmetic Logic Unit-ALU Design and Simulation

2011 International Conference on Communication Systems and Network Technologies (CSNT)

Author(s): Singh, R.R. ; Tiwari, A. ; Singh, V.K. ; Tomar, G.S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Katra, Jammu, India, India
Conference Date: 3 June 2011
Page(s): 469 - 472
ISBN (CD): 978-0-7695-4437-3
ISBN (Paper): 978-1-4577-0543-4
DOI: 10.1109/CSNT.2011.167
Regular:

VHDL environment for floating point arithmetic and logic unit design using pipelining is introduced; the novelty in the ALU design with pipelining provides a high performance ALU to execute... View More

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