IEEE - Institute of Electrical and Electronics Engineers, Inc. - Concurrent Error Detection Adder Based on Two Paths Output Computation

2011 IEEE 9th International Symposium on Parallel and Distributed Processing with Applications Workshops (ISPAW)

Author(s): Khedhiri, C. ; Karmani, M. ; Hamdi, B. ; Ka Lok Man
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2011
Conference Location: Busan, Korea (South), Korea (South)
Conference Date: 26 May 2011
Page(s): 27 - 32
ISBN (CD): 978-0-7695-4429-8
ISBN (Paper): 978-1-4577-0524-3
DOI: 10.1109/ISPAW.2011.63
Regular:

This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that... View More

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