IEEE - Institute of Electrical and Electronics Engineers, Inc. - Area efficient processing element architecture for compact hash functions systems on VIRTEX5 FPGA platform

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

Author(s): El-Hadedy, M. ; Gligoroski, D. ; Knapskog, S.J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: San Diego, CA, USA, USA
Conference Date: 6 June 2011
Page(s): 240 - 247
ISBN (Electronic): 978-1-4577-0599-1
ISBN (Paper): 978-1-4577-0598-4
ISBN (Online): 978-1-4577-0597-7
DOI: 10.1109/AHS.2011.5963943
Regular:

This paper presents the design and analysis of an area efficient processing element structure for use in cryptographic systems especially for implementing hash functions. The proposed architecture... View More

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