IEEE - Institute of Electrical and Electronics Engineers, Inc. - An improved I/O buffer correlation methodology between silicon and the SPICE model

APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Lai Chen Leong ; See Hour Ying ; Chee Seong Fong ; Wei Wei Lo
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2010
Conference Location: Kuala Lumpur, Malaysia, Malaysia
Conference Date: 6 December 2010
Page(s): 999 - 1,002
ISBN (CD): 978-1-4244-7455-4
ISBN (Electronic): 978-1-4244-7456-1
ISBN (Paper): 978-1-4244-7454-7
DOI: 10.1109/APCCAS.2010.5775098
Regular:

High-performance systems that involve tightly-constrained design parameters create significant challenges for board designers. The ability to simulate a complex design before laying out the board... View More

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