IEEE - Institute of Electrical and Electronics Engineers, Inc. - Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors

APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Pedroni, V.A. ; Jasinski, R.P. ; Pedroni, R.U.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2010
Conference Location: Kuala Lumpur, Malaysia, Malaysia
Conference Date: 6 December 2010
Page(s): 923 - 926
ISBN (CD): 978-1-4244-7455-4
ISBN (Electronic): 978-1-4244-7456-1
ISBN (Paper): 978-1-4244-7454-7
DOI: 10.1109/APCCAS.2010.5775035
Regular:

This paper describes the Panning Sorter (PanS), a new architecture for hardware implementation of compact, fast, low power data sorters operating with parallel inputs. The proposed approach is... View More

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