IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock-gated and low-power standard cell library for ISFET Two-Point Calibration processor chip

APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Wen-Yaw Chung ; Jian-Ping Chang ; Cruz, F.R.G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2010
Conference Location: Kuala Lumpur, Malaysia, Malaysia
Conference Date: 6 December 2010
Page(s): 1,163 - 1,166
ISBN (CD): 978-1-4244-7455-4
ISBN (Electronic): 978-1-4244-7456-1
ISBN (Paper): 978-1-4244-7454-7
DOI: 10.1109/APCCAS.2010.5774932
Regular:

This paper presents a novel clock gate cell that employs header and footer devices to isolate the transistor connected to clock signal. This new clock gate is called Low Internal Power Clock Gate... View More

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