IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-performance 3D-SRAM architecture design

APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Chun-Lung Hsu ; Ching-Fen Wu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2010
Conference Location: Kuala Lumpur, Malaysia, Malaysia
Conference Date: 6 December 2010
Page(s): 907 - 910
ISBN (CD): 978-1-4244-7455-4
ISBN (Electronic): 978-1-4244-7456-1
ISBN (Paper): 978-1-4244-7454-7
DOI: 10.1109/APCCAS.2010.5774741
Regular:

A high-performance three-dimension (3D) static random access memory (SRAM) architecture design is presented in this paper. The emerging 3D integration technology involves stacking two or more die... View More

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