IEEE - Institute of Electrical and Electronics Engineers, Inc. - A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2

2010 IEEE International SOC Conference (SOCC)

Author(s): Jae-Wook Yoo ; Tae-Ho Kim ; Dong-Kyun Kim ; Jin-Ku Kang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2010
Conference Location: Las Vegas, NV, USA, USA
Conference Date: 27 September 2010
Page(s): 88 - 91
ISBN (CD): 978-1-4244-6681-8
ISBN (Electronic): 978-1-4244-6683-2
ISBN (Paper): 978-1-4244-6682-5
ISSN (CD): Pending
ISSN (Paper): Pending
DOI: 10.1109/SOCC.2010.5784642
Regular:

This paper presents a clock and data recovery (CDR) circuit that supports dual data rates of 5.4Gbps and 3.24Gbps for DisplayPort v1.2 sink device. The quarter-rate linear PD in the proposed CDR... View More

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