IEEE - Institute of Electrical and Electronics Engineers, Inc. - Synchronous logic synthesis: algorithms for cycle-time minimization

Author(s): G. De Micheli
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Volume: 10
Page Count: 11
Page(s): 63 - 73
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/43.62792
Regular:

A novel approach to logic synthesis of digital synchronous circuits is presented. A model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance... View More

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