IEEE - Institute of Electrical and Electronics Engineers, Inc. - SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements

2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

Author(s): Devarapalli, S.V. ; Zarkesh-Ha, P. ; Suddarth, S.C.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2010
Conference Location: Kyoto, Japan, Japan
Conference Date: 6 October 2010
Page(s): 167 - 171
ISBN (Paper): 978-1-4244-8447-8
ISSN (Paper): 1550-5774
DOI: 10.1109/DFT.2010.27
Regular:

Aggressive device scaling has reduced the gate capacitance, which resulted in increasing sensitivity to radiation induced soft errors. In addition, technology scaling has reached to the point of... View More

Advertisement