IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and implementation of a parallel processing Viterbi decoder using FPGA

2010 International Conference on Artificial Intelligence and Education (ICAIE)

Author(s): Lei-ou Wang ; Zhe-ying Li
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2010
Conference Location: Hangzhou, China, China
Conference Date: 29 October 2010
Page(s): 77 - 80
ISBN (CD): 978-1-4244-6934-5
ISBN (Electronic): 978-1-4244-6936-9
ISBN (Paper): 978-1-4244-6935-2
DOI: 10.1109/ICAIE.2010.5641528
Regular:

Convolution encoder and Viterbi decoder are widely used in many communication systems due to the excellent error control performance. This paper deals with the design and implementation of... View More

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