IEEE - Institute of Electrical and Electronics Engineers, Inc. - Congestion-aware Network-on-Chip router architecture

2010 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS)

Author(s): Chifeng Wang ; Wen-Hsiang Hu ; Bagherzadeh, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2010
Conference Location: Tehran, Iran, Iran
Conference Date: 23 September 2010
Page(s): 137 - 144
ISBN (CD): 978-1-4244-6268-1
ISBN (Electronic): 978-1-4244-6269-8
ISBN (Paper): 978-1-4244-6267-4
DOI: 10.1109/CADS.2010.5623552
Regular:

This paper proposes a novel congestion-aware Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also... View More

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