IEEE - Institute of Electrical and Electronics Engineers, Inc. - Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips

2010 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS)

Author(s): Jahanian, A. ; Saheb Zamani, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2010
Conference Location: Tehran, Iran, Iran
Conference Date: 23 September 2010
Page(s): 107 - 114
ISBN (CD): 978-1-4244-6268-1
ISBN (Electronic): 978-1-4244-6269-8
ISBN (Paper): 978-1-4244-6267-4
DOI: 10.1109/CADS.2010.5623543
Regular:

Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a... View More

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