IEEE - Institute of Electrical and Electronics Engineers, Inc. - A novel architecture for a massively parallel low level vision processing engine on chip

2010 IEEE International Symposium on Industrial Electronics (ISIE 2010)

Author(s): Tomasi, M. ; Vanegas, M. ; Barranco, F. ; Diaz, J. ; Ros, E.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 July 2010
Conference Location: Bari, Italy, Italy
Conference Date: 4 July 2010
Page(s): 3,033 - 3,039
ISBN (CD): 978-1-4244-6391-6
ISBN (Electronic): 978-1-4244-6392-3
ISBN (Paper): 978-1-4244-6390-9
DOI: 10.1109/ISIE.2010.5637211
Regular:

Specific architectures for different low level vision modalities have been developed and described using reconfigurable hardware. Each of them tries to solve a single low level vision problem:... View More

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