IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reliability simulation of metal bump in a three-dimensional chip stacking structure

2010 11th International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP)

Author(s): Zhou Zhang ; Yuliang Deng ; Yunlong Liu ; Yufeng Jin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2010
Conference Location: Xi'an, China, China
Conference Date: 16 August 2010
Page(s): 1,218 - 1,220
ISBN (CD): 978-1-4244-8141-5
ISBN (Electronic): 978-1-4244-8142-2
ISBN (Paper): 978-1-4244-8140-8
DOI: 10.1109/ICEPT.2010.5582770
Regular:

In order to adapt the development of the Integrated circuit, a three-dimensional chip stacking structure was developed to achieve high performance, low power consumption and small packaging size.... View More

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