IEEE - Institute of Electrical and Electronics Engineers, Inc. - A study of the relationship between on-chip power distribution network voltage noise, charge per clock cycle, on-chip decoupling capacitance and clock jitter in a 40-nm field programmable gate array test chip

2010 International Workshop on Electromagnetics; Applications and Student Innovation (iWEM)

Author(s): Hui Lee Teng ; Shishuang Sun ; Man On Wong ; Boyle, P. ; Chee Seong Fong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2010
Conference Location: Taipei, Taiwan, Taiwan
Conference Date: 11 August 2010
Page(s): 75 - 79
ISBN (CD): 978-1-4244-6417-3
ISBN (Electronic): 978-1-4244-6418-0
ISBN (Paper): 978-1-4244-6416-6
DOI: 10.1109/AEM2C.2010.5578815
Regular:

As technology process nodes continue to shrink, the performance of nano-technology devices becomes increasingly dependent on power quality. With core logic voltage reduced to 0.9 V, 40-nm devices... View More

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