IEEE - Institute of Electrical and Electronics Engineers, Inc. - Long and short covering edges in combination logic circuits

Author(s): W.-N. Li ; S.M. Reddy ; S. Sahni
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 1990
Volume: 9
Page Count: 9
Page(s): 1,245 - 1,253
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/43.62769
Regular:

The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown... View More

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