IEEE - Institute of Electrical and Electronics Engineers, Inc. - A CMOS mainframe processor with 0.5- mu m channel length

Author(s): H. Schettler ; W. Haug ; K.J. Getzlaff ; C.W. Starke ; A. Bhattacharyya
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 1990
Volume: 25
Page Count: 12
Page(s): 1,166 - 1,177
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/4.62139
Regular:

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 mu m. The chip set consists of the... View More

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