IEEE - Institute of Electrical and Electronics Engineers, Inc. - A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

Author(s): T. Furuyama ; H. Ishiuchi ; H. Tanaka ; Y. Watanabe ; Y. Kohyama ; T. Kimura ; K. Muraoka ; S. Sugiura ; K. Natori
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 1990
Volume: 25
Page Count: 6
Page(s): 42 - 47
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/4.50282
Regular:

A latch-up-like failure phenomenon that shows hysteresis in the V/sub cc/-I/sub cc/ characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is... View More

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