IEEE - Institute of Electrical and Electronics Engineers, Inc. - Gate oxide effect on wafer level reliability of next generation dram transistors

2010 IEEE International Reliability Physics Symposium (IRPS)

Author(s): Yu Gyun Shin ; Kab-Jin Nam ; Heedon Hwang ; Jeong Hee Han ; Sangjin Hyun ; Siyoung Choi ; Joo-Tae Moon
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2010
Conference Location: Garden Grove (Anaheim), CA, USA, USA
Conference Date: 2 May 2010
Page(s): 282 - 286
ISBN (CD): 978-1-4244-5431-0
ISBN (Electronic): 978-1-4244-5429-7
ISBN (Paper): 978-1-4244-5430-3
ISSN (CD): 1541-7026
ISSN (Electronic): 1938-1891
ISSN (Paper): 1541-7026
DOI: 10.1109/IRPS.2010.5488817
Regular:

Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention... View More

Advertisement