IEEE - Institute of Electrical and Electronics Engineers, Inc. - Assessing chip-level impact of double patterning lithography

2010 11th International Symposium on Quality of Electronic Design (ISQED)

Author(s): Kwangok Jeong ; Kahng, A.B. ; Topaloglu, R.O.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2010
Conference Location: San Jose, CA, USA, USA
Conference Date: 22 March 2010
Page(s): 122 - 130
ISBN (CD): 978-1-4244-6455-5
ISBN (Electronic): 978-1-4244-6456-2
ISBN (Paper): 978-1-4244-6454-8
ISSN (CD): 1948-3287
ISSN (Electronic): 1948-3295
ISSN (Paper): 1948-3287
DOI: 10.1109/ISQED.2010.5450394
Regular:

Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology options such as high... View More

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