IEEE Computer Society - Parallel simulated annealing: accuracy vs. speed in placement

Author(s): M.D. Durand
Sponsor(s): IEEE Computer Society
Publisher: IEEE Computer Society
Publication Date: 1 June 1989
Volume: 6
Page Count: 27
Page(s): 8 - 34
ISSN (Paper): 0740-7475
DOI: 10.1109/54.32410

The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining... View More