IEEE - Institute of Electrical and Electronics Engineers, Inc. - A low-power calibration-free fractional-N digital PLL with high linear phase interpolator

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Fan Yang ; Hangyan Guo ; Runhua Wang ; Zherui Zhang ; Junhua Liu ; Huailin Liao
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2016
Conference Location: Toyama, Japan
Conference Date: 7 November 2016
Page(s): 269 - 272
ISBN (Electronic): 978-1-5090-3700-1
ISBN (Paper): 978-1-5090-3699-8
DOI: 10.1109/ASSCC.2016.7844187
Regular:

This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is... View More

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