IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reprogrammable redundancy for cache V min reduction in a 28nm RISC-V processor

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Brian Zimmer ; Pi-Feng Chiu ; Borivoje Nikolic ; Krste Asanovic
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2016
Conference Location: Toyama, Japan
Conference Date: 7 November 2016
Page(s): 121 - 124
ISBN (Electronic): 978-1-5090-3700-1
ISBN (Paper): 978-1-5090-3699-8
DOI: 10.1109/ASSCC.2016.7844150
Regular:

The presented processor lowers SRAM-based cache Vmin by using three architectural techniques-bit bypass (BB), dynamic column redundancy (DCR), and line disable (LD)-that use... View More

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