IEEE - Institute of Electrical and Electronics Engineers, Inc. - An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Xuqiang Zheng ; Chun Zhang ; Shuai Yuan ; Feng Zhao ; Shigang Yue ; Ziqiang Wang ; Fule Li ; Zhihua Wang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2016
Conference Location: Toyama, Japan
Conference Date: 7 November 2016
Page(s): 85 - 88
ISBN (Electronic): 978-1-5090-3700-1
ISBN (Paper): 978-1-5090-3699-8
DOI: 10.1109/ASSCC.2016.7844141
Regular:

An improved clock data recovery (CDR) operating at 40 Gb/s is implemented in 65 nm CMOS technology. Passive low-pass filters (LPFs) with adaptively adjusted bandwidth are introduced into the... View More

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