IEEE - Institute of Electrical and Electronics Engineers, Inc. - A topology-agnostic test model for link shorts in on-chip networks

2016 IEEE International Conference on Systems, Man and Cybernetics (SMC)

Author(s): Biswajit Bhowmik ; Jatindra Kumar Deka ; Santosh Biswas ; Bhargab B. Bhattacharya
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2016
Conference Location: Budapest, Hungary
Conference Date: 9 October 2016
Page(s): 4,561 - 4,566
ISBN (Electronic): 978-1-5090-1897-0
ISBN (USB): 978-1-5090-1819-2
DOI: 10.1109/SMC.2016.7844950
Regular:

With the ever-shrinking global geometries on a die and the concomitant rise in the complexity of interconnections in an on-chip network (NoC), the links used therein often suffer from various... View More

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