IEEE - Institute of Electrical and Electronics Engineers, Inc. - Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Author(s): Han Le Duc ; Chadi Jabbour ; Patricia Desgreys ; Van Tam Nguyen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2016
Conference Location: Monte Carlo, Monaco
Conference Date: 11 December 2016
Page(s): 297 - 300
ISBN (Electronic): 978-1-5090-6113-6
ISBN (USB): 978-1-5090-6112-9
DOI: 10.1109/ICECS.2016.7841191
Regular:

Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the... View More

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