IEEE - Institute of Electrical and Electronics Engineers, Inc. - Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects

2016 IEEE International Electron Devices Meeting (IEDM)

Author(s): Jhih-Yang Yan ; Sun-Rong Jan ; Yu-Jiun Peng ; H. H. Lin ; W. K. Wan ; Y.-H Huang ; Bigchoug Hung ; K.-T Chan ; Michael Huang ; M.-T Yang ; C. W. Liu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2016
Conference Location: San Francisco, CA, USA
Conference Date: 3 December 2016
ISBN (Electronic): 978-1-5090-3902-9
ISBN (USB): 978-1-5090-3901-2
ISSN (Electronic): 2156-017X
DOI: 10.1109/IEDM.2016.7838550
Regular:

A two-step pseudo isothermal plane model is used to calculate the thermal resistance of BEOL (Rth, beol). The intrinsic thermal resistances of 14nm FinFETs (Rth0, Device) are... View More

Advertisement