IEEE - Institute of Electrical and Electronics Engineers, Inc. - 32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance

2016 IEEE International Electron Devices Meeting (IEDM)

Author(s): Chi-Shuen Lee ; Brian Cline ; Saurabh Sinha ; Greg Yeric ; H.-S Philip Wong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2016
Conference Location: San Francisco, CA, USA
Conference Date: 3 December 2016
ISBN (Electronic): 978-1-5090-3902-9
ISBN (USB): 978-1-5090-3901-2
ISSN (Electronic): 2156-017X
DOI: 10.1109/IEDM.2016.7838498
Regular:

A 32-bit commercial processor core is implemented at 5-nm design rules to study transistor and interconnect technology options and the impact of increasing interconnect resistance on system... View More

Advertisement