IEEE - Institute of Electrical and Electronics Engineers, Inc. - Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

2016 IEEE International Electron Devices Meeting (IEDM)

Author(s): S. Barraud ; V. Lapras ; M. P. Samson ; L. Gaben ; L. Grenouillet ; V. Maffini-Alvaro ; Y. Morand ; J. Daranlot ; N. Rambal ; B. Previtalli ; S. Reboh ; C. Tabone ; R. Coquand ; E. Augendre ; O. Rozeau ; J. M. Hartmann ; C. Vizioz ; C. Arvet ; P. Pimenta-Barros ; N. Posseme ; V. Loup ; C. Comboroure ; C. Euvrard ; V. Balan ; I. Tinti ; G. Audoit ; N. Bernier ; D. Cooper ; Z. Saghi ; F. Allain ; A. Toffoli ; O. Faynot ; M. Vinet
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2016
Conference Location: San Francisco, CA, USA
Conference Date: 3 December 2016
ISBN (Electronic): 978-1-5090-3902-9
ISBN (USB): 978-1-5090-3901-2
ISSN (Electronic): 2156-017X
DOI: 10.1109/IEDM.2016.7838441
Regular:

We report on vertically stacked horizontal Si NanoWires (NW) /p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with... View More

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