IEEE - Institute of Electrical and Electronics Engineers, Inc. - An all-digital PLL with SAR frequency locking system in 65nm SOTB CMOS

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Author(s): Keita Arai ; Cong-Kha Pham
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2016
Conference Location: Burlingame, CA, USA
Conference Date: 10 October 2016
Page(s): 1 - 2
ISBN (Electronic): 978-1-5090-4391-0
DOI: 10.1109/S3S.2016.7804397
Regular:

This paper presents an all-digital PLL (ADPLL) which synthesizes any frequency using the successive approximation (SAR) algorithm. The proposed ADPLL consists of a high-frequency resolution... View More

Advertisement