IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter

2016 International SoC Design Conference (ISOCC)

Author(s): Hong-Jhih Chen ; Jau-Ji Jou ; Tien-Tsorng Shih
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2016
Conference Location: Jeju, South Korea
Conference Date: 23 October 2016
Page(s): 263 - 264
ISBN (Electronic): 978-1-5090-3219-8
ISBN (USB): 978-1-5090-3218-1
DOI: 10.1109/ISOCC.2016.7799778
Regular:

In this paper, a 27-1 pseudo-random bit sequence (PRBS) generator with built-in clock is designed in 0.18-μm CMOS technology. The MOS current mode logic (CML) is used in the PRBS... View More

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