IEEE - Institute of Electrical and Electronics Engineers, Inc. - A MDLL-based multi-phase clock multiplier

2016 International SoC Design Conference (ISOCC)

Author(s): Junsub Yoon ; Jongsun Kim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2016
Conference Location: Jeju, South Korea
Conference Date: 23 October 2016
Page(s): 247 - 248
ISBN (Electronic): 978-1-5090-3219-8
ISBN (USB): 978-1-5090-3218-1
DOI: 10.1109/ISOCC.2016.7799770
Regular:

A multiplying delay-locked loop (MDLL)-based multi-phase clock multiplier is presented. The proposed clock multiplier provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz... View More

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