IEEE - Institute of Electrical and Electronics Engineers, Inc. - Numerical analysis of thermal effects in SOI MOSFET Flip-Chip packages: Multi-scale studies on isolated transistors and global simulations

2016 6th Electronic System-Integration Technology Conference (ESTC)

Author(s): Giacomo Garegnani ; Vincent Fiori ; Sebastien Gallois-Garreignot ; Roberto Gonella
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2016
Conference Location: Grenoble, France
Conference Date: 13 September 2016
Page(s): 1 - 6
ISBN (Electronic): 978-1-5090-1402-6
DOI: 10.1109/ESTC.2016.7764703
Regular:

We present numerical simulations of thermal phenomena in SOI MOSFETs flip-chip packages. We consider the effects of package environment on isolated transistors performing multi-scale Finite... View More

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