IEEE - Institute of Electrical and Electronics Engineers, Inc. - Warpage reduction using dielectric layers stress tuning: From analytical model to 3D integration of large die on ceramic substrate

2016 6th Electronic System-Integration Technology Conference (ESTC)

Author(s): C. Ferrandon ; B. Kholti ; L. Castagne ; F. Casset ; R. Franiatte ; D. Mermin ; G. Simon ; G. Imbert ; S. Petitdidier ; F. Bailly ; P. Chevalier ; L. Toffanin ; N. Chevrier ; Jp Pierrel
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2016
Conference Location: Grenoble, France
Conference Date: 13 September 2016
Page(s): 1 - 6
ISBN (Electronic): 978-1-5090-1402-6
DOI: 10.1109/ESTC.2016.7764485
Regular:

A mechanical study of silicon interposer bow reduction, from wafer level manufacturing to large die stacking including analytical modeling, is presented in this paper. Indeed, understanding and... View More

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