IEEE - Institute of Electrical and Electronics Engineers, Inc. - Formal verification of fault tolerance using theorem-proving techniques

Author(s): J. Kljaich, Jr. ; B.T. Smith ; A.S. Wojcik
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Distributed Process
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 1989
Volume: 38
Page Count: 11
Page(s): 366 - 376
ISSN (Paper): 0018-9340
DOI: 10.1109/12.21123
Regular:

A formal verification system based on the use of automated reasoning techniques is described to validate fault tolerance. An extended Petri net representation, called a flow net, is described... View More

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