IEEE - Institute of Electrical and Electronics Engineers, Inc. - Impact of intermediate BEOL technology on standard cell performances of 3D VLSI

2016 46th European Solid-State Device Research Conference (ESSDERC)

Author(s): M. Brocard ; G. Berhault ; S. Thuries ; F. Clermidy ; P. Batude ; C. Fenouillet-Beranger ; L. Brunet ; F. Andrieu ; F. Deprat ; J. Lacord ; O. Rozeau ; G. Cibrario ; O. Billoint
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2016
Conference Location: Lausanne, Switzerland
Conference Date: 12 September 2016
Page(s): 218 - 221
ISBN (Electronic): 978-1-5090-2969-3
ISSN (Electronic): 2378-6558
DOI: 10.1109/ESSDERC.2016.7599625
Regular:

While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on... View More

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