IEEE - Institute of Electrical and Electronics Engineers, Inc. - Structure and software model of a parallel-vertical multi-input adder for FPGA implementation

2016 XIth International Scientific and Technical Conference on Computer Sciences and Information Technologies (CSIT)

Author(s): Ivan Tsmots ; Oleksa Skorokhoda ; Vasyl Rabyk
Sponsor(s): IEEE
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2016
Conference Location: Lviv, Ukraine
Conference Date: 6 September 2016
Page(s): 158 - 160
ISBN (Electronic): 978-1-5090-2740-8
DOI: 10.1109/STC-CSIT.2016.7589894
Regular:

In this paper parallel-vertical approach to realization of group summation has been analyzed. Analytical expression for synthesis of a 7-input single-digit adder have been realized. The structure... View More

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