IEEE - Institute of Electrical and Electronics Engineers, Inc. - Pipeline and parallel processor architecture for fast computation of 3D-DWT using modified lifting scheme

2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)

Author(s): C. Ashok Kumar ; B. K. Madhavi ; K. Lalkishore
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2016
Conference Location: Chennai, India
Conference Date: 23 March 2016
Page(s): 2,123 - 2,128
ISBN (Electronic): 978-1-4673-9338-6
ISBN (USB): 978-1-4673-9337-9
DOI: 10.1109/WiSPNET.2016.7566517
Regular:

A pipelined parallel processing 3D DWT architecture is designed in this paper based on lifting scheme algorithm with 9/7 wavelet filters. The 3D DWT architecture process a 512×512 image with 8... View More

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