IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design methodology and size limitations of submicrometer MOSFETs for DRAM application

Author(s): W.-H. Lee ; T. Osakama ; K. Asada ; T. Sugano
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 1988
Volume: 35
Page Count: 9
Page(s): 1,876 - 1,884
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/16.7400
Regular:

A design methodology of submicrometer MOSFETs for a one-transistor DRAM cell is proposed, taking into account physical limiting phenomena such as (1) avalanche breakdown at the drain junction, (2)... View More

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