IEEE - Institute of Electrical and Electronics Engineers, Inc. - A transition sequence generator for RAM fault detection

Author(s): E. Regener
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Distributed Process
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 1988
Volume: 37
Page Count: 7
Page(s): 362 - 368
ISSN (Paper): 0018-9340
DOI: 10.1109/12.2175
Regular:

In verification of n-bit CMOS memories it is usual to supply a test address sequence having n2/sup /n transitions, one for each ordered pair of n-bit words which differ in a single bit. From an... View More

Advertisement