IEEE - Institute of Electrical and Electronics Engineers, Inc. - Speed binning with high-quality structural patterns from functional timing analysis (FTA)

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

Author(s): Louis Y.-Z Lin ; Charles H.-P Wen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: Macau, China
Conference Date: 25 January 2016
Page(s): 238 - 243
ISBN (CD): 978-1-4673-9568-7
ISBN (Electronic): 978-1-4673-9569-4
ISSN (Electronic): 2153-697X
DOI: 10.1109/ASPDAC.2016.7428017
Regular:

In the nanometer era where the operating speed of a chip decides its price, design companies rely on high-qualty speed binning approaches to maxmizie their profits. The conventional speed binning... View More

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