IEEE - Institute of Electrical and Electronics Engineers, Inc. - Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in Gê+O(# of gates)

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

Author(s): Yi Diao ; Xing Wei ; Tak-Kei Lam ; Yu-Liang Wu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: Macau, China
Conference Date: 25 January 2016
Page(s): 139 - 146
ISBN (CD): 978-1-4673-9568-7
ISBN (Electronic): 978-1-4673-9569-4
ISSN (Electronic): 2153-697X
DOI: 10.1109/ASPDAC.2016.7428002
Regular:

There are situations (e.g. for reverse engineering or formal verification) circuit designers would need to extract complicated arithmetic circuitry deeply embedded inside a fully synthesized (or... View More

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